1. Field of Invention
The present invention relates to a method for manufacturing a stacked capacitor of a dynamic random access memory (DRAM). More particularly, the present invention relates to a method for manufacturing a stacked capacitor with a metalinsulator-metal structure.
2. Description of Related Art
A semiconductor memory, such as a DRAM, mainly consists of a transistor and a capacitor. Therefore, improvement in the efficiency of these two structures tends to be the direction in which technology is developing.
When the semiconductor enters the deep sub-micron process, the size of the device becomes smaller. For the conventional DRAM structure, this means that the space used by the capacitor becomes smaller. Since computer software is gradually becoming huge, even more memory capacity is required. In the case where it is necessary to have a smaller size with an increased capacity, the conventional method of fabricating the DRAM capacitor needs to change in order to fulfil the requirements of the trend.
There are two approaches at present for reducing the size of the capacitor while increasing its memory capacity. One way is to select a high-dielectric material, and the other is to increase the surface area of the capacitor.
There are two main types of capacitor that increase capacitor area. These are the deep trench-type and the stacked-type, where the deep trench-type capacitor is formed by digging out a trench with a depth of 6-7 .mu.m and filling the trench with a conductive layer, a capacitive dielectric layer and a conductive layer in sequence for the capacitor.
The stacked capacitor is a principal method of fabricating the conventional semiconductor capacitor. As this is related to long-term semiconductor capacitor technology, most of the semiconductor manufacturers, such as Micron in USA, NEC in Japan and Samsung in Korea, have developed technology for such a capacitor.
Although crown-type, fin-type, cylinder-type or spread-type capacitor can fit the requirement for forming a DRAM with a relatively high density, it is difficult to form these various capacitors with a capacity of about 256 megabits (Mb) and even more than 40 giga bit (Gb) under the limitation of the design rule.
Accordingly, it is important to use a dielectric layer with a relatively high dielectric constant in the stacked capacitor. In the current process technique, tantalum oxide (Ta.sub.2 O.sub.5) with a dielectric constant of about 25 and barium titanate (BaTiO.sub.3) with a dielectric constant higher than about a hundred are popular dielectric materials possessing a relatively high dielectric constant.
When a dielectric material with a relatively high dielectric constant is used in a stacked capacitor, the materials for manufacturing the upper and the bottom electrodes need to be gradually replaced in order to enhance the performance of the capacitor. A structure known as a metal-insulator-metal (MIM) structure possesses a low-interfacial reaction specificity to enhance the performance of the capacitor. Therefore, it has become an important topic of research for the semiconductor capacitor in the future.
FIGS. 1A through 1B are schematic, cross-sectional views of the conventional process for manufacturing a stacked capacitor with a MIM structure.
As shown in FIG. 1A, an oxide layer 102 is formed on a substrate 100. A patterning process is performed to form a storage node contact hole 104 in the oxide layer 102. A polysilicon plug 106 is formed in the storage node contact hole 104.
The method for forming a polysilicon plug 106 comprises steps of forming a polysilicon layer on the oxide layer 102 and to fill the storage node contact hole 104, and then removing a portion of the polysilicon layer above the oxide layer 102 by etching back.
A metal barrier layer 108 and a metal layer 110 are formed on the oxide layer 102 and the polysilicon plug 106 in sequence. The metal layer 110 is made of platinum (Pt).
As shown in FIG. 1B, a photolithography and etching process is performed to pattern the metal layer 110 and the metal barrier layer 108 to form a patterned metal layer 110a and a patterned metal barrier layer 108a. The patterned metal layer 110a and the patterned metal barrier layer 108a together form a storage node 112 of a bottom electrode.
A dielectric layer 114 with a high dielectric constant and a metal layer 116 are formed on the storage node 112 and the oxide layer 102 in sequence. The dielectric layer 114 is made of barium strontium titanate (BaSrTiO.sub.3, BST) and is used as a capacitor dielectric layer in the capacitor. The metal layer 116 is used as an upper electrode of a capacitor and is made of Pt.
After the stacked capacitor with high capacitance is formed, the subsequent processes for manufacturing a DRAM are well known to people skilled in the art, so these procedures will not be described herein.
However, Pt is very expensive and the minimum thickness of a Pt layer is limited to increase the surface area of the bottom electrode of the capacitor. Therefore, the cost of the process is high. Incidentally, in the process for patterning Pt, since Pt is difficult to etch by dry etching and the minimum thickness of Pt layer is limited, the critical dimension (CD) is extremely difficult to control.
Moreover, when the BST layer with a high dielectric constant is formed on the storage node, in order to maintain the dielectric specificity of BST, the BST layer is formed in an environment full of oxygen. However, the conductivity of the metal barrier layer is lost as the metal barrier layer is oxidized, and the reliability of capacitor is decreased.
Furthermore, the junction between the BST layer and the metal barrier layer is a low schottky barrier. Therefore, the dielectric leakage current is large if the BST layer electrically contacts the metal barrier layer.